1. Field of the Invention
This invention is related to an application specific semiconductor integrated circuit (ASIC) and its manufacturing method thereof, and in particular is related to an application specific semiconductor integrated circuit which uses an automatic placement and routing system which automatically places a wire as well as a via-hole which connects circuits using a computer, and its manufacturing methods.
2. Description of the Related Art
An application specific semiconductor integrated circuit is a semiconductor device which is best suited to a high mix low volume production. In the application specific semiconductor integrated circuit, an automatic placement and routing system using a computer, is used in the placement of wires which carry out wire connection and the placement of a via-hole which connects upper and lower wires within the placement of a circuits (function block) such as a logical circuit or memory circuit manufactured by a floor plan.
Recently, as the miniaturization of line and space, which refers to the relationship between the width of wires and the interval between wires, as well as the miniaturization of the semiconductor elements which make up a circuit, progresses, there is a tendency for design rules which are handled in an automatic placement and routing system to become more complex. For example, there is a tendency for a multi-space rule in which an adjacent wire interval changes in accordance with a wire width, or a contact overlay margin rule in which the size of the contact overlay margin area around a via-hole changes in accordance with a wire width, are to be included as new rules.
These rules which are included in design rules are important rules when actually manufacturing an application specific semiconductor integrated circuit using a production mask which is made for use in production from mask data which is produced based upon an automatic placement and routing system. A wire which is automatically placed using an algorithm of an automatic placement and routing system is placed in high density (dense) in the central part of an application specific semiconductor integrated circuit and in low density (non-dense) in the surrounding part. In the manufacture of an actual application specific integrated circuit, an aluminum alloy film, for example, is used in a wire, and this aluminum alloy film is patterned by etching and using a photo-mask which is produced by photo lithography technology after the film is formed by a spattering method. If the density of the wires is different a change occurs in the wrap-around of the development solution when a photo-mask is manufactured and in the etching solution when patterning the aluminum alloy film. Usually, the width of a wire which is placed in the part where wire density is high increases because the wrap-around of the developing solution or etching solution is insufficient. However, the width of a wire which is placed in the part where wire density is low decreases because the darting of the developing solution or etching solution is sufficiently carried out.
The multi space rule is a rule in which a wire interval between a wire with a large width and an adjacent wire is increased and a wire interval between a wire with a small width and an adjacent wire is reduced in order to resolve defects during this type of manufacture process. Alternatively, the contact overlay margin rule is a rule in which the wire width around a via-hole of a wire in which poor conduction can easily occur is increased in the case where an adjacent wire interval is wide.
Further, this kind of application specific semiconductor integrated circuit and its manufacturing methods are disclosed in, for example, Japanese Patent Laid-Open Publication No. 2001-85614.
However, in the application specific semiconductor integrated circuit and its manufacturing methods previously stated, the following points were not considered. In an automatic placement and routing system the multi-space rule fixes the wire width and wire interval and the contact overlay margin rule fixes the contact overlay margin size around the via-hole of the wire. It is preferred that uniform design rules are adopted. However, in whichever wire placement pattern or via-hole placement pattern, in the case where a design rule is selected so that a deign rule check (DRC) error does not occur, the wire layout area after wire placement increases and because the number of wires which can be placed per area unit therefore decreases, the integration of the application specific semiconductor integrated circuit decreases.